Switching converters such as the buck converter shown in FIG. 1 are generally known in the current state of the art. Said converter comprises an MOS transistor 1 having a non-drivable terminal coupled to an input voltage Vin and another non-drivable terminal coupled to the cathode of an asynchronous rectifier diode D1 having its anode coupled to ground GND; the transistor is driven by a control device 2. The cathode of the diode D1 is coupled to a low-pass filter comprising an inductor L and capacitor C from whose ends the converter output voltage Vout is drawn.
In conditions of operation with the continuous conduction mode (CCM), that is when the current in the inductor L never goes to zero, and with a resistive type of load LOAD, if the transistor 1 has an “on” time Ton and an “off” time Toff, where T=Ton+Toff, it follows that Vout=D*Vin where D is the duty cycle given by D=Ton/T. In conditions of operation with the discontinuous conduction mode (DCM), that is when the current in the coil goes to zero during the switching period, the output voltage Vout is a function of the value of the inductor L, time period T, duty cycle D and input voltage Vin, i.e.
  Vout  =            2      ⁢      Vin              1      +                        (                      1            +                                                            8                  ⁢                  L                                                  R                  ⁢                                                                          ⁢                  T                                            *                              1                                  D                  2                                                              )                2            where R is the resistive value of the load LOAD.
Another buck converter layout is shown in FIG. 2. The converter comprises a first MOS transistor HS having a non-drivable terminal coupled to the input voltage Vin and another non-drivable terminal P coupled to a terminal of the inductor L and a non-drivable terminal of a second MOS transistor LS coupled to ground GND. The other terminal of inductor L is coupled to the capacitor C, having its other terminal coupled to ground GND; the capacitor C is placed in parallel with the load LOAD and a resistive divider comprising a series of two resistors, R1 and R2. A fraction VFB of the output voltage Vout is input to a control device 20. The transistors HS and LS are switched on in a push-pull mode and as a result there is a lower power dissipation, given that the voltage drop at the ends of the transistor LS is lower than the voltage drop on the diode.
The control device 20 comprises a first circuit 24 comprising in turn a comparator for comparing the voltage VFB with a reference voltage Vref and means able to effect a pulse width modulation (PWM) in response to said comparison. The control device 20 comprises two drive circuits or drivers 21 and 22 receiving as inputs the PWM signals output by the circuit 24 and able to drive the transistors HS and LS via the signals HSIDE and LSIDE. The driver 22 is powered by a voltage Vccdr whereas driver 21 is powered by a voltage Vcb originating from a bootstrap circuit 23 comprising a capacitor Cboot situated between the node P and the cathode of a diode Dcb having its anode coupled to the voltage Vccdr.
When the converter is switched on, the node P is grounded GND and the capacitance Cboot is charged to the voltage Vccdr−Vd where Vd is the voltage drop of the diode Dcb. When a pulse arrives from the PWM signal output by circuit 24, driver 21 starts to charge the gate of the HS transistor, supplying a charge Q drawn from the capacitance Cboot. When the HS transistor is switched on, the node P is brought to the voltage Vin and the voltage Vcb is forcibly brought to the voltage Vin+Vcboot where Vcboot is the voltage at the ends of the capacitor Cboot. In this condition the driver 21 supplies a voltage to the gate of the HS transistor that is sufficient to keep it on. The switching cycle concludes with the switching off of the transistor HS, whose gate is brought to the voltage of the node P. When the transistor LS is switched on, the node P is again brought to ground GND and the capacitance Cboot is thus recharged via the diode Dcb.
In switching periods where the node P is not brought to ground GND, the capacitor Cboot, non-recharged, tends to become discharged due to leakage currents and the charging of the capacitance Cgs of the transistor HS. In the event of a sequence of consecutive cycles in which this occurs, the capacitor Cboot may become discharged to a point where the voltage is no longer sufficient to enable the HS transistor to be switched on.
Such a situation occurs when the device operates with a duty cycle D=1 or when the converter is unable to discharge the current of the inductor L and a residual output current remains; in the latter case, when the device is switched on, the voltage to at the node P is equal to the voltage Vout. In either case the voltage Vgs between the source and gate of the HS transistor will not be sufficient to switch it on.